- Papers can be submitted using the following link: Click here
- Papers should strictly adhere to the IEEE conference formatting guidelines using the templates available at Click here.
- The conference papers should not exceed 6 pages including references. In accordance with the IEEE policy, Plagiarism in any form, at any level, is unacceptable. IEEE policy on Plagiarism can be found at Click here.
- Authors are requested to carefully upload the co-authors, no authors will be included or excluded at the later stage.
AVARTA
The First International Conference on Advanced VLSI Design, AI Solutions, and Reconfigurable Technology Applications (AVARTA 2026) is set to be a groundbreaking global forum, bringing together brilliant minds from academia, industry, and research to shape the future of semiconductor and AI-driven technologies. This premier event will serve as a catalyst for innovation, collaboration, and transformative breakthroughs across a spectrum of emerging domains, including Machine Learning & Artificial Intelligence, Reconfigurable Computing & Processor Design, Analog & RF Circuits, Embedded Security, Semiconductor & Circuit Design, Embedded Systems, IoT & Cyber-Physical Systems, and Optical & Quantum Computing. AVARTA 2026 aims to redefine the possibilities of intelligent systems, fostering cutting-edge discussions and technological advancements that will drive the future of VLSI and AI solutions. Join us as we push the boundaries of technology and unlock the next era of intelligent computing!
About SASTRA
A sprawling campus with a vibrant population of students, faculty and state-of-the-art laboratories has made SASTRA a landmark in the educational map of India. SASTRA has reached national standing in terms of academic performance, co-curricular and extra-curricular activities. SASTRA offers various Undergraduate, Postgraduate and Doctoral programmes in Engineering, Arts, Science, Law and Management. The excellence of the academic programmes offered by the University is replicated in the ratings awarded by National Assessment and Accreditation Council (NAAC) which has reaccredited SASTRA with a maximum grade of A++ (3.76/4.00) in cycle IV, retaining the status of Category-I University.
School of Computing
The school has highly sophisticated computing facilities and state-of-the-art laboratories for training and R&D work in various areas of Computer science & Information Technology applications. As part of R&D, the Centre named TIFAC-CORE has been established with a supercomputer, VLSI & Embedded System lab, Sun Lab, etc., The School is equipped with 1 petaflops HPC which comprises 1 head node & 30 compute nodes with NVIDIA Tesla A100 GPU cards. The Centre is set up to promote triangular linkage between Industry, Academics, and Government in the IT field. The faculty members have a good blend of industry and teaching experience.
Conference Themes
Machine Learning & Artificial Intelligence
- Advanced algorithms for supervised, unsupervised, reinforcement learning
- Deep learning architectures and their applications
- Explainable AI and interpretable models
- Federated learning for decentralized systems
- AI and ML for edge computing, IoT, and cloud integration
- Real-time analytics using AI-driven methods
- AI-enhanced cybersecurity, privacy preservation techniques, and healthcare
- Deployment of AI in reconfigurable hardware, generative AI, ethical AI, and bias mitigation
Reconfigurable Computing & Processor Design
- Autonomous/adaptable/reconfigurable systems and architectures
- FPGA Accelerator Design
- Placement & Routing of FPGA layout
- High-performance, energy-efficient multi-core and many-core (heterogeneous) processor architectures
- Microarchitecture design techniques for single-threaded and multi/many-core processors, such as instruction-level parallelism, pipelining, caches, branch prediction, multithreading, and networks-on-chip
- Techniques for low-power, secure, and reliable processor architectures
- Hardware acceleration for emerging applications including NVM, quantum, neuromorphic, bio-inspired
- Hardware support for processor virtualization
- Real-life design challenges: case studies, tradeoffs, retrospectives, HW/SW prototyping and emulation on FPGAs
- Application driven heterogeneous computing platforms
- Chiplets based Heterogeneous system design
Analog & Mixed Signal and RF circuits
- Amplifiers, comparators, oscillators, filters, references; nonlinear analog circuits; digitally-assisted analog circuits
- Analog design at lower technology nodes, Analog Circuits for Various Applications, Data Converters, High Speed Interfaces
- RF, mmWave and THz transceivers, SoCs, and SiPs
- Frequency synthesizers, system architecture for 5G and 6G wireless, next generation systems for radar, sensing, and imaging
- Reliability aspects in RFICs
Power & Energy Management
- Power management and control circuits, regulators; power converter ICs, energy harvesting circuits and systems
- Wideband gap topologies and gate-drivers
- Power and Signal isolators
- Power management for automotive systems, battery management circuits and systems
Embedded Systems, IoT, Cyber Physical Systems & Automotie Systems
- Embedded Systems Language (ESL)
- System-level design methodology
- Concurrent interconnect
- Networks-on-chip
- Defect-tolerant architectures
- Hardware/Software co-design and co-verification
- Reconfigurable computing
- Embedded Multicores and Multiprocessor System on a Chip (MPSoC)
- Real-time embedded systems
- Embedded software including Operating Systems, Firmware, Middleware; Communication, virtualization, encryption, compression, security, reliability
- Embedded systems for automotive and Electric Vehicles (EVs)
- Edge intelligence
- Artificial Intelligence of Things (AIoT)
- Design automation for IoT/CPS
- MedTech devices and systems, RISC-V based systems. Sensor Interfacing, Instrumentation, Biomedical Circuits and Healthcare Systems
- Low Noise Circuits, EMI Immune Design, Auto Calibration Techniques, Wearable Electronics, flexible electronics, ultra-low power circuit techniques, circuits
- AgriTech Systems, Robotics, and systems for IoT
Optical & Quantum Computing
- Quantum Machine Learning (QML)
- Variational Quantum Algorithms (VQE, QAOA)
- Quantum Simulation for Materials & Chemistry
- Quantum Programming Frameworks (Qiskit, Cirq, Braket)
- Quantum Control and Calibration Techniques
- Superconducting Qubits and Trapped Ion Systems
- Cryogenic Electronics for Quantum Systems
- Quantum-Classical Co-design Architectures
- FPGA/ASIC Acceleration for Quantum Control
- Neuromorphic and Brain-Inspired Computing
- Post-Quantum Cryptography (PQC)
- Quantum-Resistant Hardware Architectures
- Side-Channel Attacks in Quantum/Hybrid Systems
- Secure Hardware for Quantum Key Distribution (QKD)
- Silicon Photonics for High-Speed Computing
- Optical Neural Networks
- Photonic AI Accelerators
- Plasmonics and Nanophotonic Devices
Speakers
Prof. Amlan Chakrabarti
A. K. Choudhury
School of Information technology,
University of Calcutta, India
Dr. V. Nagarajan
Conference Chair,
IEEE Madras Section
Dr. V. Veerappan
Co-Founder and president of Tessolve Semiconductor Pvt. Ltd.
Prof. Neng-Tien Huang
Yuan Ze University,
Taiwan
Prof. Cheng Hsiao Wu
Missouri University of Science & Technology,
USA
Paper Submission
AVARTA 2026 invites authors to submit their original research and findings in the form of technical paper for the single blind peer process. Prospective authors are requested to submit original papers that have not been published elsewhere.
Papers on the following tracks are invited:
- Track 1: Machine Learning & Artificial Intelligence
- Track 2: Reconfigurable Computing & Processor Design
- Track 3: Analog, Mixed Signal & RF circuits
- Track 4: Embedded Security
- Track 5: Semiconductors, Logic & Circuit Design
- Track 6: Embedded Systems, IoT, Cyber-Physical Systems & Automotive Systems
- Track 7: Optical & Quantum Computing
Registration
Registration Guidelines: Click here
| Category | Indian Delegates (INR) | Foreigh Delegates (USD) | ||
|---|---|---|---|---|
| IEEE | Non-IEEE | IEEE | Non-IEEE | |
| Academia | ₹ 8260 | ₹ 9440 | $ 200 | $ 250 |
| Industry | ₹ 10620 | ₹ 11800 | $ 300 | $ 350 |
| Attendees | ₹ 3540 | ₹ 4130 | $ 100 | $ 150 |
*** Inclusive of 18% GST
Payment
Account Name: DDP FPGA 2023
Account No.: 500101013492489
IFSC Code: CIUB0000528
MICR Code: 613054014
Branch Code: 000528
Bank: City Union Bank Ltd
Branch: Thirumalaisamudram Branch, SASTRA University, Thanjavur
Paper Submission Deadline
18/08/2026
Notification
28/08/2026
Camera Ready Submission & Registration
15/09/2026
Organizing Committee
Chief Patrons
Prof. R. Sethuraman
Chancellor,
SASTRA Deemed University,
India
Dr. S. Vaidhyasubramaniam
Vice-Chancellor,
SASTRA Deemed University,
India
Patrons
Dr. R. Chandramouli
Registrar,
SASTRA Deemed University,
India
Dr. S. Swaminathan
Dean – P&D,
SASTRA Deemed University,
India
General Chairs
Dr. V. S. Shankar Sriram
Dean - SOC,
SASTRA Deemed University,
India
Dr. R. John Bosco Balaguru
Dean - S/R,
SASTRA Deemed University,
India
Dr. K. Sridhar
Dean - Research,
SASTRA Deemed University,
India
Dr. P. Sakthivel
Chairman,
IEEE Madras Section,
India
Convenor / Co-Convenors
Dr. R. Muthaiah
AD-Research - SoC
SASTRA Deemed University,
India
Convenor
Dr. K. Ramkumar
AD-Academics - SoC
SASTRA Deemed University,
India
Co-Convenor
Dr. D. Manivannan D
AD-Infrastructure - SoC
SASTRA Deemed University,
India
Co-Convenor
Dr. R. Alageswaran
AD-Student Welfare - SoC
SASTRA Deemed University,
India
Co-Convenor
Organizing Chairs
- Dr. R. Sivaraman,
SoC, SASTRA Deemed University, India - Dr. D. Muralidharan,
SoC, SASTRA Deemed University, India - Dr. V. Venkatesh,
SoC, SASTRA Deemed University, India - Dr. R. Ananth Hari,
SoC, SASTRA Deemed University, India
TPC Chairs
- Dr. R. Ezhilarasie,
SoC, SASTRA Deemed University, India - Dr. K. Hariharan,
SoC, SASTRA Deemed University, India - Dr. M.V. Rajilal,
SoC, SASTRA Deemed University, India - Dr. T. Pasupathi,
SoC, SASTRA Deemed University, India
Publicity Chairs
- Dr. S. Ramakrishnan,
SoC, SASTRA Deemed University, India - Dr. S. Ramya,
SoC, SASTRA Deemed University, India - Dr. M. Ifjaz Ahmed,
SoC, SASTRA Deemed University, India - Dr. H. Anila Glory,
SoC, SASTRA Deemed University, India - Dr. V. Nirmala,
SoC, SASTRA Deemed University, India
Panel Chairs
- Dr. Joseph Abraham Sundar,
SoC, SASTRA Deemed University, India - Dr. J. Premaladha,
SoC, SASTRA Deemed University, India - Dr. R. Saravanan,
SoC, SASTRA Deemed University, India - Dr. J. Ramya,
SoC, SASTRA Deemed University, India
IEEE Madras Section
Advisory Committee
- Dr.S.Radha,
Secretary, IEEE Madras Section - Dr.S.Brindha,
Treasurer, IEEE Madras Section - Dr.V.Nagarajan,
Conference Chair, IEEE Madras Section - Dr.T.Shanmuganatham,
Vice Chairman Academics, IEEE Madras Section - Dr.Ramalatha Marimuthu,
Vice Chairman Industry, IEEE Madras Section
Steering
Committee
- Dr. K. Neelakantan,
Former – Director, ANURAG, India - Dr. G. Lakshmi Narayanan,
NIT Trichy, India - Dr. G. Seetharaman,
Indian Institute of Information Technology Tiruchirappalli. - Dr. Debdutta Ray,
Indian Institute of Technology Madras, Chennai. - Dr. Jayaraj U Kidav,
NIELIT Aurangabad - Dr. C. Pethuru Raj,
Edge AI Division, Reliance Jio Platforms Ltd. - Dr. M. Sabarimalai Manikandan,
Indian Institute of Technology, Palakkad. - Dr. V. Masilamani,
IIITDM, Kancheepuram - Dr. M. Bhaskar,
NIT Trichy, India - Dr. S. Moorthi,
NIT Trichy, India - Mr. K. Padmanaban,
Altera-Intel, India - Dr. Shriram Kris Vasudevan,
Intel, India - Dr. R. Sundararaman,
Turing Enc, India - Mr. G. B. Ramprakash,
Enix Technologies India Pvt., Ltd., India
International Advisory Committee
- Dr. Cheng-Hsiao Wu,
Missouri University of Science and Technology, USA - Dr. Bijaya Shrestha,
Missouri University of Science and Technology, USA - Dr. Gelli Ravikumar,
Iowa State University, USA - Dr. Li Yuxuan,
Yuan Ze University, Taiwan - Dr. Lin Chenghong,
Yuan Ze University, Taiwan - Dr. Eugene Song,
Asia University, Taiwan - Dr. Pandi Divya,
Asia University, Taiwan - Dr. Sriram Vaisambhayana,
Nanyang Technological University, Singapore - Dr. Wenfeng Zhao,
Binghamton University, NY, USA - Dr. Chinnaiyan Senthilpari,
Multimedia University, Malaysia. - Dr. Shankar Deepak Srinivasan,
Rolls Royce Deutschland & Co KG, Blankenfelde-Mahlow, Germany
National Advisory Committee
- Dr. R. Hariprakash,
Secretary, IEEE Madras Section - Dr. S. Radha,
IEEE Madras Section - Dr. K. Prabu,
National Institute of Technology Karnataka, Surathkal - Dr. N Ramasubramanian,
NIT Trichy, India - Dr. C. Mala,
NIT Trichy, India - Dr. R. Dhanalakshmi,
Indian Institute of Information Technology, Tiruchirappalli. - Mrs. A. Suganya,
Society for Electronic Transactions and Security, Chennai - Dr. V. Subramaniyasamy,
Vellore Institute of Technology, Vellore - Dr. Sudhish N George,
National Institute of Technology, Calicut - Dr. E. Papanasam,
Vellore Institute of Technology, Chennai - Dr. Madhusudhana Rao Nalluri,
Amrita Vishwa Vidhya Peetham, AP, India - Dr. R. Bharanidharan,
SRM University, Chennai, India
Conference Schedule
will be updated soon!...